 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a High Efficiency Synchronous Step-Down Switching Regulators ADP1148, ADP1148-3.3, ADP1148-5 FUNCTIONAL BLOCK DIAGRAM ADJUSTABLE VERSION PWR SIGNAL VIN P-DRIVE N-DRIVE GND GND SENSE(+) VFB SENSE(-) 3 1 14 12 11 8 9 7 FEATURES Operation From 3.5 V to 18 V Input Voltage Ultrahigh Efficiency > 95% Low Shutdown Current Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over Wide Current Range Logic Controlled Micropower Shutdown Short Circuit Protection Very Low Dropout Operation Synchronous FET Switching for High Efficiency Adaptive Nonoverlap Gate Drives APPLICATIONS Notebook and Palmtop Computers Portable Instruments Battery Operated Digital Devices Industrial Power Distribution Avionics Systems Telecom Power Supplies GPS Systems Cellular Telephones GENERAL DESCRIPTION ADP1148 NON-OVERLAP DRIVE 2 SLEEP 1 QR S R QS V B C 10mV to 150mV VIN SENSE(-) VFB 6 10 S VTH2 VTH1 T 13k G 1.25V 100k OFF-TIME CONTROL 4 REFERENCE 5 CT ITH SHUTDOWN INT VCC The ADP1148 is part of a family of synchronous step-down switching regulator controllers featuring automatic sleep mode to maintain high efficiencies at low output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250 kHz using a constant off-time current-mode architecture. The constant off-time architecture maintains constant ripple current in the inductor, easing the design of wide input range converters. Current-mode operation provides excellent line and load transient response. The operating current level is user programmable via an external current sense resistor. The ADP1148 incorporates automatic Power Saving Sleep Mode operation when load currents drop below the level required for continuous operation. In sleep mode, standby power is reduced to only about 2 mW at VIN = 10 V. In shutdown, both MOSFETs are turned off. TYPICAL APPLICATIONS VIN (5.2V TO 18V) + 1F 10nF VIN INT VCC P-DRIVE P-CH IRF7204 L* RSENSE** 62 H 0.05 VOUT 5V/2A SENSE(+) 1000pF RC 1k CC 3300pF CT 470pF S-GND CT SENSE(-) N-DRIVE P-GND N-CH IRF7403 C1 10BQ040 *COILTRONICS CTX-68-4 **KRL SL-1-C1-0R050L + COUT 390 F EFFICIENCY - % CIN 100 F + 100 VIN = 6V 95 VIN = 10V 90 0V = NORMAL >1.5V = SHUTDOWN ADP1148 SHUTDOWN ITH 85 80 75 FIGURE 1 CIRCUIT 70 0.02 0.2 LOAD CURRENT - A 2 Figure 1. High Efficiency Step-Down Converter Figure 2. ADP1148-5 Typical Efficiency REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997 ADP1148, ADP1148-3.3, ADP1148-5-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (0 C T +70 C, A 1 VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.) Min 1.21 Typ 1.25 0.2 Max 1.29 1.0 3.43 5.2 +40 Units V A V V mV Parameter FEEDBACK VOLTAGE ADP1148 Only FEEDBACK CURRENT ADP1148 Only REGULATED OUTPUT VOLTAGE ADP1148-3.3 ADP1148-5 OUTPUT VOLTAGE LINE REGULATION OUTPUT VOLTAGE LOAD REGULATION ADP1148-3.3 ADP1148-5 SLEEP MODE OUTPUT RIPPLE INPUT DC SUPPLY CURRENT Normal Mode Sleep Mode (ADP1148-3.3) Sleep Mode (ADP1148-5) Shutdown 3 Symbol V10 I10 VOUT Conditions2 VIN = 9 V VIN = 9 V ILOAD = 700 mA ILOAD = 700 mA TA = +25C, VIN = 7 V to 12 V, ILOAD = 50 mA 3.23 4.9 -40 3.33 5.05 dVOUT dVOUT 5 mA < ILOAD < 2 A 5 mA < ILOAD < 2 A dVOUT IQ ILOAD = 0 A TA = +25C VIN = 4 V < V IN < 18 V VIN = 4 V < V IN < 18 V VIN = 4 V < V IN < 18 V VSHUTDOWN = 2.1 V, 4 V < VIN < 15 V V9 = VOUT/4 + 25 mV (Forced), V7 = 5 V, TA = +25C V9 = VOUT/4 mV - 25 mV (Forced), V7 = 5 V V7 = VOUT + 100 mV (Forced) V7 = VOUT - 100 mV (Forced) V7 = VOUT + 100 mV (Forced V7 = VOUT - 100 mV (Forced) TA = +25C 0 V < VSHUTDOWN < 8 V, VIN = 18 V TA = +25C, VOUT in Regulation, V7 = VOUT, VOUT = 0 V CT = 390 pF, ILOAD = 700 mA CL = 3000 pF (Pins 1, 14) VIN = 6 V, TA = +25C 50 4 40 60 50 1.6 160 160 10 65 100 mV mV mV p-p 2.3 250 250 20 mA A A A CURRENT SENSE THRESHOLD VOLTAGE4 ADP1148 Only ADP1148-3.3 ADP1148-5 SHUTDOWN PIN THRESHOLD ADP1148-3.3, ADP1148-5 SHUTDOWN PIN INPUT CURRENT CT PIN DISCHARGE CURRENT V8-V7 25 130 130 130 0.6 150 25 150 25 150 0.8 1.2 65 2 5 100 170 170 170 2.0 5 90 10 6 200 mV mV mV mV mV mV V A A A s ns V10 I10 I4 OFF-TIME DRIVER OUTPUT TRANSITION TIMES tOFF tR, tF NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Quality Control methods. Specifications subject to change without notice. 2 TJ is calculated from the ambient temperature T A and power dissipation P D according to the following formulas: ADP1148AR, ADP1148AR-3.3, ADP1148AR-5: T J = T A + (PD x 110C/W) ADP1148AN, ADP1148AN-3.3, ADP1148AN-5: T J = T A + (PD x 70C/W) 3 Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power dissipation at high input voltages. 4 The ADP1148 version is tested with external feedback resistors, setting the nominal output voltage to 3.3 V. Specifications subject to change without notice. -2- REV. A ADP1148, ADP1148-3.3, ADP1148-5 ELECTRICAL CHARACTERISTICS (-40 C T Parameter FEEDBACK VOLTAGE ADP1148 Only REGULATED OUTPUT VOLTAGE ADP1148-3.3 ADP1148-5 INPUT DC SUPPLY CURRENT3 Normal Mode Sleep Mode (ADP1148-3) Sleep Mode (ADP1148-5) Shutdown CURRENT SENSE THRESHOLD VOLTAGE4 ADP1148 Only Symbol V10 VOUT A +85 C, VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.) Min 1.20 3.17 4.85 Typ 1.25 3.33 5.05 1.6 160 160 10 Max 1.30 3.4 5.2 2.6 280 280 24 Units V V V mA A A A 1 Conditions2 VIN = 9 V VIN = 9 V ILOAD = 700 mA ILOAD = 700 mA VIN = 4 V < V IN < 18 V VIN = 4 V < V IN < 18 V VIN = 6 V < V IN < 18 V VSHUTDOWN = 2.1 V, 4 V < VIN < 12 V IQ V8-V7 V9 = VOUT/4 + 25 mV (Forced), V7 = 5 V V9 = VOUT/4 - 25 mV (Forced), V7 = 5 V V7 = VOUT + 100 mV (Forced) V7 = VOUT - 100 mV (Forced) V7 = VOUT + 100 mV (Forced) V7 = VOUT - 100 mV (Forced) V10 0.55 tOFF CT = 390 pF, ILOAD = 700 mA 4 0.8 5 2 6.2 V s 0 115 150 0 150 0 150 175 mV mV mV mV mV mV ADP1148-3.3 ADP1148-5.0 SHUTDOWN PIN THRESHOLD ADP1148-3.3, ADP1148-5 OFF-TIME 115 115 175 175 NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Quality Control method. 2T is calculated from the ambient temperature T and power dissipation P according to the following formulas: J A D ADP1148AR, ADP1148AR-3, ADP1148AR-5: T J = TA + (PD x 110C/W) ADP1148AN, ADP1148AN-3, ADP1148AN-5: T J = TA + (PD x 70C/W) 3Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power dissipation at high input voltages. 4The ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 V. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Input Supply Voltage (Pin 3) . . . . . . . . . . . . . -0.3 V to +20 V Continuous Output Currents (Pins 1, 14) . . . . . . . . . . 50 mA Sense Voltages (Pins 7, 8) . . . . . . . . . . . . . . . . -0.3 V to VCC Operating Temperature Range . . . . . . . . . . . . 0C to +70C Extended Commercial Temperature Range . . -40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C Model ADP1148AN ADP1148AR ADP1148AN-3.3 ADP1148AR-3.3 ADP1148AN-5 ADP1148AR-5 Output Voltage ADJ ADJ 3.3 V 3.3 V 5V 5V Package Description Plastic DIP Small Outline Package Plastic DIP Small Outline Package Plastic DIP Small Outline Package Package Option N-14 SO-14 N-14 SO-14 N-14 SO-14 REV. A -3- ADP1148, ADP1148-3.3, ADP1148-5 PIN FUNCTION DESCRIPTIONS Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic P-Channel Drive NC VIN CT Int VCC ITH Sense- Sense+ VFB Shutdown Signal GND Power GND NC Function High Current Gate Drive for Top P-Channel MOSFET. The voltage swing at Pin 4 is from VIN to ground. No Connection. Input Voltage. External Capacitor CT from Pin 4 to Ground Sets the Operating Frequency. The frequency is also dependent on the ratio VOUT/VIN. Internal Supply Voltage, Nominally 3.3 V. Must be decoupled to signal ground. Do not externally load this pin. Error Amplifier Decoupling Point. The current comparator threshold increases with the Pin 7 voltage. Connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5 versions. Pin 7 is also the (-) input for the current comparator. The (+) Input for the Current Comparator. A built-in offset between Pins 7 and 8, in conjunction with RSENSE, sets the current trip threshold. For the ADP1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider used to set the output voltage. On ADP1148-3.3 and ADP1148-5 versions, this pin is not used. Taking Pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both MOSFETs off. Must be at ground potential for normal operation. Small Signal Ground. Must be routed separately from other grounds to the (-) terminal of COUT. Driver Power Ground. Connects to source of N-channel MOSFET and the (-) terminal of CIN. No Connection. N-Channel Drive High Current Drive for bottom N-channel MOSFET. The voltage swing at Pin 13 is from ground to VIN. PIN CONFIGURATIONS 14-Lead Plastic DIP 14-Lead Plastic SO P-DRIVE 1 NC 2 VIN 3 CT 4 INT VCC 5 14 N-DRIVE 13 NC ADP1148 12 POWER GND TOP VIEW 11 SIGNAL GND (Not to Scale) 10 SHUTDOWN 9 8 VFB* SENSE(+) ITH 6 SENSE(-) 7 NC = NO CONNECT *FIXED OUTPUT VERSIONS = SD1 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. A Typical Performance Characteristics-ADP1148, ADP1148-3.3, ADP1148-5 200 1000 VSENSE = VOUT = 5V 1000 L = 50 H RSENSE = 0.02 L = 25 H RSENSE = 0.02 800 150 CAPACITANCE - pF 800 RSENSE - m COUT - F 600 600 100 400 VIN = 7V 200 VIN = 12V 400 L = 50 H RSENSE = 0.05 50 VIN = 10V 200 0 0 1 2 3 4 5 0 0 MAXIMUM OUTPUT CURRENT - A 100 200 FREQUENCY - kHz 300 0 0 1 2 3 4 (VIN-VOUT) VOLTAGE - V 5 Figure 3. Selecting RSENSE vs. Maximum Output Current Figure 4. Operating Frequency vs. Timing Capacitor Value Figure 5. Selecting Minimum Output Capacitor vs. (VIN-VOUT ) and Inductor 100 I 2R GATE CHARGE EFFICIENCY/LOSS - % 95 100 98 96 94 EFFICIENCY - % 92 90 88 86 84 82 FIGURE 1 CIRCUIT ILOAD = 100mA ILOAD = 1A VOUT - mV +40 +20 IQ 90 0 ILOAD = 0.1A -20 ILOAD = 1A -40 FIGURE 1 CIRCUIT -60 85 80 0.01 0.03 0.1 0.3 1.0 OUTPUT CURRENT - A 3.0 80 0 4 8 12 16 INPUT VOLTAGE - V 20 0 4 6 8 VIN 10 12 14 16 Figure 6. Typical Efficiency Losses Figure 7. Efficiency vs. Input Voltage Figure 8. ADP1148-5 Output Voltage Change vs. Input Voltage 60 FIGURE 1 CIRCUIT 40 SUPPLY CURRENT - mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 SLEEP MODE 0.2 0.0 ACTIVE MODE 30 25 SUPPLY CURRENT - A 20 VOUT - mV VIN = 6V 20 VSHUTDOWN = 2V 15 0 -20 VIN = 12V -40 -60 10 5 0 0 0.5 1.0 1.5 2.0 LOAD CURRENT - A 2.5 4 6 8 10 12 14 16 INPUT VOLTAGE - V 18 20 4 6 8 10 12 14 16 INPUT VOLTAGE - V 18 20 Figure 9. Load Regulation Figure 10. DC Supply Current Figure 11. Supply Current in Shutdown REV. A -5- ADP1148, ADP1148-3.3, ADP1148-5-Typical Performance Characteristics 1.8 GATE CHARGE CURRENT - mA 30 80 70 60 OFF TIME - sec 1.6 NORMALIZED FREQUENCY 1.4 1.2 0C 25 25 C 70 C 20 Qn+Qp = 100nC 15 50 40 30 5V 20 3.3V 10 1.0 0.8 0.6 0.4 0.2 0.0 1 2 4 6 8 (VIN-VOUT) - V 10 12 10 Qn+Qp = 50nC 5 0 20 80 110 140 170 200 230 260 50 OPERATING FREQUENCY - kHz 0 0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.3 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE - V Figure 12. Operating Frequency vs. (VIN-VOUT ) Figure 13. Gate Charge Supply Current Figure 14. Off Time vs. VOUT 155 150 SENSE VOLTAGE - mV 145 MAXIMUM THRESHOLD 140 135 130 125 120 0 85 25 70 TEMPERATURE - C 100 Figure 15. Current Sense Threshold Voltage -6- REV. A ADP1148, ADP1148-3.3, ADP1148-5 APPLICATIONS The ADP1148 uses a current-mode, constant off-time structure to switch a pair of external complementary N- and P-channel MOSFETs. The operating frequency of the device is determined by the value of the external capacitor connected to the CT pin. The output voltage is sensed by an internal voltage divider which is connected to the Sense(-) pin (ADP1148-3.3 and AD1148-5) or an external voltage divider returned to VFB (ADP1148). A voltage comparator V, and a gain block G compare the values of the divided output voltage with a reference voltage of 1.25 V. To maximize the efficiency, the ADP1148 automatically switches between two operational modes, power-saving and continuous. The Flip-Flop 1 is the main control element when the device is in its power-saving mode while the gain block is the main control when the output voltage moves to continuous mode. During the continuous mode of the PMOS switch on-cycle, the current comparator C, monitors the voltage between Sense(-) and Sense(+). When the voltage level reaches the threshold level, the P drive output is switched to VIN which turns off the P-channel MOSFET. The timing capacitor CT is now able to discharge at a rate determined by the off-time controller. The discharge current is made to be proportional to the value of the output voltage (measured at the Sense(-) pin) to model the inductor current which decays at a rate which is proportional to the output voltage. While the timing capacitor is discharging, the N drive output goes to VIN , turning on the N-channel MOSFET. When the voltage level on the timing capacitor has discharged to the threshold voltage level VTH1, comparator T switches setting Flip-Flop 1. This forces the N drive to go off and the P drive output low and subsequently turns the P-channel MOSFET on. The sequence is then repeated. As load current increases, the output voltage starts to reduce. This results in the output of the gain circuit increasing the level of the current comparator threshold, thus tracking the load current. At very low load currents the power-saving sequence will be interrupted by the Set of Flip-Flop 2, by voltage comparator B, which also monitors the voltage across RSENSE. When the load current decreases to half the designed inductor ripple current, the voltage across RSENSE will reverse polarity. When this happens, comparator B will set the Q-bar output of Flip-Flop 2, which will go to logic zero state and interrupt the cycle-by-cycle operation and inhibit the output FET-driver. The output of the power supply storage capacitor will slowly be drained by the load and the output voltage starts decreasing. When this decreased voltage exceeds the VOS of comparator V, this in turn will reset Flip-Flop 2, and normal cycle-by-cycle operation will resume. If the load is very small, it will take a long time for FlipFlop 2 to reset, and during that time the oscillator capacitor may discharge below VTH2. At the point at which the timing capacitor discharges below VTH2, comparator S trips causing the internal sleep-bar to go low. The circuit is now in sleep mode and the N-channel Power MOSFET remains turned off. While the circuit remains in this mode, a significant amount of the circuit of the IC is turned off dropping the ground current from approximately 1.6 mA to a level of 160 A. In this state the load current is supplied by the output capacitor. The sleep mode is also terminated by the reset of Flip-Flop 2. *Component, voltage, current, etc., values are in SI-units (international standard) unless otherwise indicated. To prevent both the external MOSFETs from ever being turned on simultaneously, feedback is incorporated to sense the state of the driver output pins. Before the N drive output can go high, the P drive output must also be high. Likewise, the P drive output is unable to go low while the N drive output is high. By utilizing a constant off-time structure, the device operation is a function of the input voltage. To limit the effect of frequency variation as the device approaches dropout, the controller begins to increase the discharge current as V IN drops below VOUT +1.5 V. While the device is in dropout, the P-channel MOSFET is on constantly. RSENSE Selection For Output Current The choice of RSENSE is based on the required output current. The ADP1148 current comparator has a threshold range which extends from 0 mV to a maximum of 150 mV/RSENSE. The current comparator threshold sets the peak of the inductor current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. The ADP1148 operates effectively with values of RSENSE from 20 m to 200 m. A graph for selecting RSENSE versus maximum output current is given in Figure 3. Solving for RSENSE and allowing a margin for variations in the ADP1148 and external component values yields: RSENSE = 100 mV/IMAX The peak short circuit current, (ISC(PK) ) tracks IMAX. Once RSENSE has been chosen, ISC(PK) can be predicted from the following equation: ISC(PK) = 150 mV/RSENSE The load current, below which power-saving mode commences (IPOWER-SAVING) is determined by the offset in comparator B and the value of the inductor chosen. Comparator B is designed to have approximately 5 mV offset. This offset and the inductor can now be used to predict the power saving mode current as follows: IPOWER-SAVING ~ 5 mV/RSENSE + VO x tOFF /2 L The ADP1148 automatically extends tOFF during a short circuit to provide adequate time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short circuit current, ISC(AVG), to be lowered to approximately IMAX. L and C T Selection for Operating Frequency The ADP1148 uses a constant off-time architecture with tOFF determined by an external timing capacitor CT . Each time the P-channel MOSFET switch turns on, the voltage on CT is reset to approximately 3.3 V. During the off time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the current in inductor L, which likewise decays at a rate proportional to VOUT. Therefore, the inductor value must track the timing capacitor value. The value of CT is calculated from the preferred continuous mode operating frequency: CT = 1/2.6 x 104 x f Assumes VIN = 2 VOUT (Figure 1 circuit). A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 5. REV. A -7- ADP1148, ADP1148-3.3, ADP1148-5 As the operating frequency is increased, the gate charge losses will cause reduced efficiency (see Efficiency section). The full formula for operating frequency is given by: f = ( 1 - VOUT/VIN )/tOFF where tOFF = 1.3 x 104 x CT x VREG /VOUT. VREG is the desired output voltage (i.e., 5 V or 3.3 V), VOUT is the measured output voltage. Thus, VREG/VOUT = 1 in regulation. Note that as VIN reduces, the frequency also decreases. When the input to output voltage differential drops below 1.5 V, the ADP1148 reduces tOFF by increasing the discharge current in CT. This prevents audible operation before the device goes into dropout. Once the frequency has been set by CT , the inductor L must be chosen to provide no more than 25 mV/RSENSE of peak-to-peak inductor ripple current. This is set by the equation: 25 mV xt V = OUT OFF LMIN RSENSE components are also available from Coiltronics which do not increase the component height significantly. Power MOSFET Two external power MOSFETs must be selected for use with the ADP1148, a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage VGS(TH) and on resistance RDS(ON) . The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. When logic-level MOSFETs are used, the ADP1148 supply voltage must be less than the absolute maximum VGS rating for the MOSFETs (e.g., > 8 V of IRF7304. The maximum output current IMAX determines the RDS(ON) requirement for the two power MOSFETs. When the ADP1148 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. The duty cycles for the MOSFET and diode are given by: P-Channel Duty Cycle = VOUT/VIN N-Channel Duty Cycle = (VIN - VOUT)/VIN From the duty cycle the required RDS(ON) for each MOSFET can be derived: P-Ch RDS(ON) = (VIN x PP )/[VOUT x IMAX2 x (1 + dP )] N-Ch RDS(ON) or LMIN = V OUT x tOFF x RSENSE 25 mV Substituting for tOFF from above gives the minimum required inductor value of: LMIN = 5.1 x 105 x RSENSE x CT x VREG As the inductor value increases above the minimum value, the ESR requirements for the output capacitor are relaxed at the expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A result of this occurrence will be that the ADP1148 may not be in power saving mode operation and efficiency will be significantly reduced at low currents. Inductor Core = (VIN x PN)/[(VIN - VOUT) x IMAX2 x (1+dN)] Once the minimum value for L is known, the selection of the inductor must be made. High efficiency converters - generally cannot accommodate the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy (MPP), or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss, so design goals can focus on copper loss and preventing saturation. Ferrite core material saturates "hard," which causes the inductance to collapse abruptly when the peak design current is exceeded. This results in a sharp increase in inductor ripple current and subsequently output voltage ripple which can cause the power saving mode operation to be falsely triggered in the ADP1148. To prevent this action from occurring, do not allow the core to saturate! Molypermalloy from Magnetics, Inc., is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. Many new designs for surface mount All trademarks are the property of their respective holders. where Pp and PN are the allowable power dissipations and dp and dN are the temperature dependency of RDS(ON). PP and PN will be determined by efficiency and/or thermal requirements (see Efficiency). (1+d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. temperature curve, but d = 0.007/C can be used as an approximation for low voltage MOSFETs. The Schottky diode D1 shown in Figure 1 conducts only during the deadtime between the conduction of the two power MOSFETs. D1's purpose is to prevent the body-diode of the N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. D1 should be selected for forward voltage of less than 0.5 V when conducting IMAX. C IN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VlN . To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: CIN required IRMS ~ [VOUT(VIN - VOUT)]0.5 x IMAX/VIN This formula has a maximum at VIN = 2 VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. -8- REV. A ADP1148, ADP1148-3.3, ADP1148-5 An additional 0.1 F - 1 F ceramic bypass capacitor is advised on VIN Pin 3 parallel with CIN. The selection of COUT is driven by the required effective series resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the ADP1148: COUT required ESR < 2 RSENSE. Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2 RSENSE, the efficiency degrades by less than 1%. Manufacturers such as Sprague, and United Chemmicon should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor has the lowest ESR for its size, at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface-mount applications multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface-mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Consult the manufacturer for other specific recommendations. The CO output filter capacitor has to be sized correctly to avoid excessive ripple voltages at low frequencies. See Figure 5 for output capacitor selection. Transient Response Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ADP1148 circuits: 1) ADP1148 dc bias current, 2) MOSFET gate charge currents, 3) I2 x R losses. 1) The dc supply current is the current which flows into VIN Pin 3 less the gate charge current. For VIN = 10 V the ADP1148 dc supply current is 160 A for no load, and increases proportionally with load up to a constant 1.6 mA after the ADP1148 has entered continuous mode. Because the dc bias current is drawn from VIN, the resulting loss increases with input voltage. For VIN = 10 V the dc bias losses are generally less than 1% for load currents over 30 mA. However, at very low load currents the dc bias current accounts for nearly all of the loss. 2) MOSFET gate charge currents result from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN which is typically much larger than the dc supply current. In continuous mode, IGATECHG = f (QP + QN). The typical gate charge for a 100 m N-channel power MOSFET is 25 nC and for the P-channel about twice that value. This results in IGATECHG = 7.5 mA in 100 kHz continuous operation for a 2% to 3% typical midcurrent loss with VIN = 10 V. Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using a larger MOSFET than necessary to control I2 x R losses. 3) I2 x R losses are easily predicted from the dc resistances of the MOSFET, inductor, and current shunt. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the P-channel and Nchannel MOSFETs. If the two MOSFETs have about the same RDS(ON), the resistance of one MOSFET can be simply summed with the resistances of L and RSENSE to obtain I2 x R losses. For example, if each RDS(ON) = 100 m, RL = 150 m, and RSENSE = 50 m, then the total resistance is 300 m. This results in losses ranging from 3% to 10% as the output current increases from 0.5 A to 2 A. I2 x R losses cause the efficiency to roll-off at high output currents. Figure 6 shows how the efficiency losses in a typical ADP1148 regulator. The gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region. If power saving mode operation was not employed at low currents, the gate charge loss alone would cause the efficiency to drop to unacceptable levels. With power saving mode operation, the dc supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output current is reduced. As expected, the I2 x R losses dominate at high load currents. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses, Schottky conduction losses during deadtime and inductor core losses, generally account for less than 2% total additional loss. The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in dc (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to D1LOAD x ESR, where ESR is the effective series resistance of COUT. D1LOAD also begins to charge or discharge COUT until the regulator loop adapts to the current change and returns VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The external components on the ITH pin shown in the Figure 1 circuit will prove adequate compensation for most applications. A second, more severe transient is caused by switching in loads with large (>1 mF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the inrush current to these capacitors below the current limit of the circuit. Efficiency The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% - (L1 + L2 + L3 +. . . ) where L1, L2, etc. are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) REV. A -9- ADP1148, ADP1148-3.3, ADP1148-5 Design Example Output Crowbar As a design example, assume VIN = 12 V (nominal), VOUT = 5 V, IMAX = 2 A, and f = 200 kHz, RSENSE. C T, and L can immediately be calculated: RSENSE = 100 mV/2 = 50 m t OFF = (1/200 kHz) x [1 - (5/12)] = 2.92 s CT = 2.92 s/(1.3 x 104) = 220 pF L min = 5.1 x 105 x 50 E-3 x 220 pF x 5 V = 28 H Assume that the MOSFET dissipations are to be limited to PN = 2PP = 250 mW. If TA = 50C and the thermal resistance of each MOSFET is 50C/W, then the junction temperatures will be 63C and dP = dP = 0.007 x (63-25) = 0.27. The required RDS(ON) for each MOSFET can now be calculated: P-Ch RDS(ON) = 12 x 0.25/5 x 2 x 1.27 = 120 m N-Ch RDS(ON) = 12 x 0.25/7 x 2 x 1.27 = 85 m The P-channel requirement can be met by a IRF7204. The N-channel requirement can be met by a IRF7404. Note that the most stringent requirement for the N-channel MOSFET is with VOUT = 0 (i.e., short circuit). During a continuous short circuit, the worst case N-channel MOSFET dissipation rises to: PN ~ ISC(AVG)2 x RDS(ON) x (1 + dN) With the 50 m sense resistor I SC(AVG) = 2 A will result, increasing the N-channel dissipation to 0.45 W at die temperature of 73C. CIN will require an rms current rating of at least 1 A at temperature, and COUT will require an ESR of 50 m for optimum efficiency. Now allow VIN to drop to its minimum value. At lower input voltages, the operating frequency will decrease and the Pchannel will be conducting most of the time causing the power dissipation to increase. At VIN(MIN) = 7 V, the frequency shifts to: fMIN = (1 - VOUT/VIN)/t OFF = (1/2.92 s) x (1 - 5/7) = 98 kHz and the P-channel power dissipation increases to: PP = (120 m) (2 A)2 (1.27) 5 V/7 V = 435 mW This last step is needed to ensure the maximum temperature of the P-channel MOSFET is not exceeded. ADP1148 Adjustable Applications An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. Pulling the timing cap CT pin above 1.5 V when the output voltage is greater than the desired regulated value will turn "on" the N-channel MOSFET and turn "off" the P-channel MOSFET. A fault condition such as an external short between VIN and VOUT, or an internal short of the P-channel device which causes the output voltage to go above a maximum allowable value can be detected by external circuity. Turning on the N-channel MOSFET when this fault is detected will cause large currents to flow and blow the system fuse. The N-channel MOSFET needs to be sized so it will safely handle this over current condition. The typical delay from pulling the CT pin high and the N drive, Pin 14 going high is 250 ns. Note: under shutdown conditions, the N-channel MOSFET is held OFF and pulling the CT pin high will not cause the N-channel MOSFET to crowbar the output. A simple N-channel FET can be used as an interface between the overvoltage detect circuitry and the ADP1148 as shown in Figure 16. 5 *FROM CROWBAR DETECT CIRCUIT VN2222LL 4 *ACTIVE WHEN VGATE = VIN OFF WHEN VGATE = GROUND INT VCC ADP1148 CT Figure 16. Output Crowbar Interface Troubleshooting Since efficiency is critical to ADP1148 applications, it is very important to verify that the circuit is functioning correctly in both continuous and power saving mode operation. The waveform to monitor is the voltage on the timing capacitor CT pin. In continuous mode (ILOAD > IPOWER SAVING MODE ), the voltage on the CT pin should be a sawtooth with a 0.9 V p-p swing. This voltage should never dip below 2 V as shown in Figure 17a. When load currents are low (ILOAD < IPOWER SAVING MODE), power saving mode operation occurs. The voltage on the CT pin now falls to ground for periods of time as shown in Figure 17b. If the CT pin is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout list. 3.3V 0V (A) CONTINOUS MODE OPERATION When an output voltage other than 3.3 V or 5 V is required, the ADP1148 adjustable version is used with an external resistive divider from VOUT to VFB Pin 9. The regulated voltage is determined by: VOUT = 1.25 (1 + R2/R1) To prevent a stray pickup, a 100 pF capacitor is suggested across R1 located close to the ADP1148. Auxiliary Windings 3.3V 0V (B) POWER-SAVING MODE The ADP1148 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. -10- Figure 17. CT Waveforms REV. A ADP1148, ADP1148-3.3, ADP1148-5 Board Layout When laying out the printed circuit board, the following check list should be used to ensure proper operation of the ADP1148. These items are also illustrated graphically in the layout diagram of Figure 18. Check the following in your layout: 1) Are the signal and power grounds segregated? The ADP1148 SIGNAL GND (Pin 11) must return to the (-) plate of COUT. The power ground returns to the source of the N-channel MOSFET, anode of the Schottky diode, and (-) plate of CIN, which should have as short lead lengths as possible. 2) Does the ADP1148 SENSE(-), (Pin 7), connect to a point close to RSENSE and the (+) plate Of COUT? In adjustable versions the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. 3) Are the SENSE(-) and SENSE(+) leads routed together with minimum PC trace spacing? The 1000 pF capacitor between Pins 7 and 8 should be as close as possible to the ADP1148. 4) Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? This capacitor provides the ac current to the P-channel MOSFET. 5) Is the input decoupling capacitor (1 F) connected closely between VIN (Pin 3) and POWER GND (Pin 12)? This capacitor carries the MOSFET driver peak currents. 6) Is INTVCC (Pin 5) decoupled with a 10 nF capacitor to signal ground? 7) Is the SHUTDOWN (Pin 10) actively pulled to ground during normal operation? The Shutdown pin is high impedance and must not be allowed to float. To prevent noise spikes from erroneously tripping the current comparator, a 1000 pF capacitor is needed across Sense(-) and Sense(+). P-CHANNEL D1 CIN VIN - 1 P-DRIVE N-DRIVE 14 N-CHANNEL 2 NC 1F 3 4 CT 10nF 3300pF 5 6 7 NC 13 ADP1148 VIN CT INT VCC ITH SENSE(-) POWER GND SIGNAL GND SHUTDOWN VFB SENSE(+) 12 11 10 9 8 R2 L - R1 COUT VOUT RSENSE 1k 1000pF NC = NO CONNECT R1, R2 OUTPUT DIVIDER REQUIRED FOR ADJUSTABLE VERSION ONLY. Figure 18. ADP1148 Layout Diagram (See Board Layout) REV. A -11- ADP1148, ADP1148-3.3, ADP1148-5 VIN 4V TO 18V CIN 100 F 20V IRF7204 D1 10BQ040 IRF7403 1 2 1F 3 4 CT 300pF 10nF CC 3300pF RC 1k 5 6 7 14 13 12 11 10 9 8 1000pF **RSENSE 0.1 COUT 220 F 10V 2 AVX VOUT 3.3V/1A *L 50 H P-DRIVE NC N-DRIVE NC ADP1148-3.3 VIN CT INT VCC ITH SENSE(-) POWER GND SIGNAL GND SHUTDOWN VFB SENSE(+) NC = NO CONNECT *COILTRONICS CTX50-2-MP **KRL SP-1/2-A1-0R100J Figure 19. ADP1148 Low Dropout, 3.3 V/1 A High Efficiency Regulator VIN 4V TO 9V CIN 220 F 20V IRF7204 D1 10BQ015 IRF7403 1 2 1F 3 4 CT 560pF 10nF CC 6800pF RC 1k 5 6 7 14 13 12 11 10 9 8 1000pF NC = NO CONNECT *COILTRONICS CTX50-2-MP **KRL SL-1-C1-0R05J **RSENSE 0.05 75k 1% 200pF 25k 1% COUT 220 F 10V VOUT -5V/1.4A *L 50 H P-DRIVE NC VIN CT INT VCC ITH SENSE(-) N-DRIVE NC ADP1148 POWER GND SIGNAL GND SHUTDOWN VFB SENSE(+) 2 Figure 20. 4 V to 9 V Input Voltage to -5 V/1.4 A Regulator -12- REV. A ADP1148, ADP1148-3.3, ADP1148-5 VIN 5.2V TO 14V CIN 100 F 20V IRF7204 D1 10BQ040 IRF7403 1 2 1F 3 4 CT 390pF 10nF CC 3300pF RC 1k 5 6 7 P-DRIVE NC VIN CT INT VCC ITH SENSE(-) N-DRIVE NC 14 13 12 11 10 9 8 1000pF **RSENSE 0.05 R2 56k 1% 100pF R1A 33k 1% R1B 43k 1% *L 50 H ADP1148 VN2222LL 0V: VOUT = 3.3V 5V: VOUT = 5V POWER GND SIGNAL GND SHUTDOWN VFB SENSE(+) COUT 220 F 10V 2 OS-CON VOUT 3.3V/2A OR 5V/2A NC = NO CONNECT *COILTRONICS CTX50-2-MP **KRL SL-1-C1-0R050J Figure 21. Logic Selectable 5 V/1 A or 3.3 V/2 A High Efficiency Regulator REV. A -13- ADP1148, ADP1148-3.3, ADP1148-5 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N-14) 0.795 (20.19) 0.725 (18.42) 14 1 8 7 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC SEATING PLANE 0.015 (0.381) 0.008 (0.204) 14-Lead Plastic SO (SO-14) 0.3444 (8.75) 0.3367 (8.55) 14 1 8 7 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45 0.0099 (0.25) SEATING PLANE 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) -14- REV. A -15- -16- C2219a-2-12/97 PRINTED IN U.S.A. |
Price & Availability of ADP1148
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |